Tegra: memctrl_v1: disable AHB redirection after cold boot

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direct
path to the IRAM, the MC implements AHB redirection during boot to allow
path to IRAM. In this mode, accesses to a programmed memory address aperture
are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
initialized to disable this aperture. Once bootup is complete, we must
program IRAM base/top, thus disabling access to IRAM.

This patch provides functionality to disable this access. The tegra port
calls this new function before jumping to the non-secure world during
cold boot.

Signed-off-by: Varun Wadekar <[email protected]>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
index 859ecd53edbd7e5f506e48a402a55a74bd1cdc21..fc7072737f7629c8961b345fae289deca6d9cab5 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
@@ -218,3 +218,29 @@ done:
        video_mem_base = phys_base;
        video_mem_size = size_in_bytes >> 20;
 }
+
+/*
+ * During boot, USB3 and flash media (SDMMC/SATA) devices need access to
+ * IRAM. Because these clients connect to the MC and do not have a direct
+ * path to the IRAM, the MC implements AHB redirection during boot to allow
+ * path to IRAM. In this mode, accesses to a programmed memory address aperture
+ * are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
+ * is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
+ * initialized to disable this aperture.
+ *
+ * Once bootup is complete, we must program IRAM base to 0xffffffff and
+ * IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then
+ * potentially accessible in this address range. These aperture registers
+ * also have an access_control/lock bit. After disabling the aperture, the
+ * access_control register should be programmed to lock the registers.
+ */
+void tegra_memctrl_disable_ahb_redirection(void)
+{
+       /* program the aperture registers */
+       tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF);
+       tegra_mc_write_32(MC_IRAM_TOP_LO, 0);
+       tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0);
+
+       /* lock the aperture registers */
+       tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
+}

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index d3c3e873ae7e606e39c286309fa7d337c98ce5d4..7cf54b512118277f4be5d3676aaf7c230c88eaf9 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -581,3 +581,11 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
         */
        mce_update_gsc_videomem();
 }
+
+/*
+ * This feature exists only for v1 of the Tegra Memory Controller.
+ */
+void tegra_memctrl_disable_ahb_redirection(void)
+{
+       ; /* do nothing */
+}

diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 9e7e576c2c4b761613216583de66190ae162aaf6..d2a6be56fe643089c4e81c33c117f568405c914c 100644 (file)
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -299,7 +299,16 @@ void bl31_platform_setup(void)
  ******************************************************************************/
 void bl31_plat_runtime_setup(void)
 {
-       ; /* do nothing */
+       /*
+        * During boot, USB3 and flash media (SDMMC/SATA) devices need
+        * access to IRAM. Because these clients connect to the MC and
+        * do not have a direct path to the IRAM, the MC implements AHB
+        * redirection during boot to allow path to IRAM. In this mode
+        * accesses to a programmed memory address aperture are directed
+        * to the AHB bus, allowing access to the IRAM. This mode must be
+        * disabled before we jump to the non-secure world.
+        */
+       tegra_memctrl_disable_ahb_redirection();
 }
 
 /*******************************************************************************

diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h
index a3f08755acf8c5bbd87a48547b3ebd5e6e1c1d19..1557bbf887605fef61516a33376c4d2c92e49a5a 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -36,5 +36,6 @@ void tegra_memctrl_restore_settings(void);
 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
 void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
 void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
+void tegra_memctrl_disable_ahb_redirection(void);
 
 #endif /* __MEMCTRL_H__ */

diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h
index b504594bf05069077b4c2908f85dd33fa2f9249c..8b8ce793c17669ba2581365ece0834d40903d98d 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl_v1.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h
@@ -60,6 +60,13 @@
 #define MC_SMMU_TRANSLATION_ENABLE_4_0         0xb98
 #define  MC_SMMU_TRANSLATION_ENABLE            (~0)
 
+/* MC IRAM aperture registers */
+#define MC_IRAM_BASE_LO                                0x65CU
+#define MC_IRAM_TOP_LO                         0x660U
+#define MC_IRAM_BASE_TOP_HI                    0x980U
+#define MC_IRAM_REG_CTRL                       0x964U
+#define  MC_DISABLE_IRAM_CFG_WRITES            1U
+
 static inline uint32_t tegra_mc_read_32(uint32_t off)
 {
        return mmio_read_32(TEGRA_MC_BASE + off);